1. Field of the Invention
The present invention relates, in general, to the compensation of a position of a main picture being displayed on a screen of a monitor of a television receiver (referred to hereinafter as TV), and more particularly to a circuit and a method for compensating for the position of the main picture in which the main picture and a sub-picture are displayed on the adjacent portions of the screen in a picture-in-picture (referred to hereinafter as PIP) mode, respectively, as if in a picture-out-picture (referred to hereinafter as POP) mode.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a block diagram of a conventional video processing circuit for a TV. As shown in this drawing, the conventional video processing circuit comprises a sub-picture intermediate frequency (referred to hereinafter as IF) processor 1 for separating a sub-picture video signal SA and a sub-picture synchronous signal SB from an IF signal SIF of a sub-picture inputted therein, and a sub-picture video processor 2 for analog/digital-converting the sub-picture video signal SA from the sub-picture IF processor 1, reducing an aspect ratio of the digitized sub-picture video signal, digital/analog-converting the digitized sub-picture video signal of the reduced aspect ratio and applying the resultant sub-picture video signal to a chroma circuit 6.
An on-screen display (referred to hereinafter as OSD) signal generator 3 is adapted to generate OSD color signals Ro, Go and Bo in response to a control signal from a microcomputer 5.
The microcomputer 5 is adapted to generate the control signal and control data in response to a key input signal from a key matrix unit 4, and output the control signal and the control data to the OSD signal generator 3 and the sub-picture video processor 2, respectively. The control data from the microcomputer 5 is information regarding vertical and horizontal positions of the sub-picture to display together with a main picture on a screen of a color picture tube (referred to hereinafter as CPT) 7.
The chroma circuit 6 is adapted to switch an external main picture video signal SC, the sub-picture video signal from the sub-picture video processor 2 and the OSD color signals Ro, Go and Bo from the OSD signal generator 3 to output a composite picture video signal to the CPT 7. Also, the chroma circuit 6 separates main picture vertical and horizontal synchronous signals VS and HS from the main picture video signal SC and outputs the separated main picture vertical and horizontal synchronous signals VS and HS to the sub-picture video processor 2 as signal SD.
A deflection controller 8 is adapted to generate horizontal and vertical deflection control currents in response to the main picture horizontal and vertical synchronous signals HS and VS, and output the generated horizontal and vertical deflection control currents to the CPT 7 to control a beam scanning direction of the CPT 7 for the display of the output from the chroma circuit 6 on the screen of the CPT 7.
The operation of the conventional video processing circuit with the above-mentioned construction will hereinafter be described.
Upon selection of a PIP-ON key on the key matrix unit 4 by the user, a corresponding signal is applied to the microcomputer 5. Then, the microcomputer 5 recognizes the PIP-ON key signal inputted therein, and outputs the control data regarding the vertical and horizontal positions of the sub-picture to display on the screen of the CPT 7 to the sub-picture video processor 2. In response to the control data from the microcomputer 5, the sub-picture video processor 2 analog/digital-converts the sub-picture video signal SA from the sub-picture IF processor 1, reduces the aspect ratio of the digitized sub-picture video signal, digital/analog-converts the digitized sub-picture video signal of the reduced aspect ratio and applies the resultant sub-picture video signal to the chroma circuit 6.
The chroma circuit 6 receives the main picture video signal SC, the sub-picture video signal from the sub-picture video processor 2 and the OSD color signals Ro, Go and Bo from the OSD signal generator 3, and outputs the composite picture video signal to the CPT 7 for the display thereon.
The deflection controller 8 generates the horizontal and vertical deflection control currents in response to the main picture horizontal and vertical synchronous signals HS and VS, and outputs the generated horizontal and vertical deflection control currents to the CPT 7. As a result, the beam scanning direction of the CPT 7 is controlled by the horizontal and vertical deflection control currents from the deflection controller 8, thereby causing the composite picture video signal from the chroma circuit 6 to be displayed on the screen of the CPT 7.
On the other hand, the sub-picture video processor 2 receives, serially, the sub-picture display vertical and horizontal data from the microcomputer 5. Then, the sub-picture video processor 2 counts the received sub-picture display horizontal and vertical data synchronously with the main picture horizontal and vertical synchronous signals HS and VS from the chroma circuit 6. As a result of the counting, the sub-picture video processor 2 outputs the sub-picture video signal to the chroma circuit 6. Therefore, the sub-picture is displayed in the position on the screen of the CPT 7 corresponding to the sub-picture display vertical and horizontal data from the microcomputer 5.
In the case where the PIP-ON key is selected by the user, the sub-picture is displayed on the screen, being superimposed on a part of the main picture. For this reason, the main picture is partially hidden by the sub-picture on the screen in a PIP mode as shown in FIG. 5A. To solve this problem, the main and sub-pictures can be displayed on the left and right portions of the screen in a POP mode as shown in FIG. 5B, respectively. However, in this case, a right edge portion of the main picture is hidden by the sub-picture. As a result, the center of the main picture appears shifted to the right on the screen.